Digital prototype of LLRF system for SSRF

ZHAO Yu-Bin; YIN Cheng-Ke; ZHANG Tong-Xuan; FU Ze-Chuan; ZHAO Zhen-Tang; DAI Zhi-Min; LIU Jian-Fei; WANG Fang

doi:10.1088/1674-1137/32/9/015

Chinese Physics C> 2008, Vol. 32> Issue(9) : 758-760 DOI: 10.1088/1674-1137/32/9/015

Digital prototype of LLRF system for SSRF

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Abstract：
This paper describes a field programming gate array (FPGA) based low level radio frequency (LLRF) prototype for the SSRF storage ring RF system. This prototype includes the local oscillator (LO), analog front end, digital front end, RF out, clock distributing, digital signal processing and communication functions. All feedback algorithms are performed in FPGA. The long term of the test prototype with high power shows that the variations of the RF amplitude and the phase in the accelerating cavity are less than 1% and 1° respectively, and the variation of the cavity resonance frequency is controlled within ±10 Hz.

References

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. Lawrence Doolittle et al. Operational Performance of the SNS LLRF Interim System. Proceeding of the 2003 Particle Accelerator Conference. 1464-14662. Liepe M et al. A New Digital Control System for CESR-Cand the Connell ERL. PAC 2003, Portland, 20033. Wojciech M. Zabolotny et al. Design and Simulation ofFPGA Implementation of RF Control System for Tesla TestFacility. 2003-084. Garoby R. Low Level RF and Feedback CERN PS/RF5. Anton Rohlev. CERN LINAC LLRF. LLRF2005 Workshop CERN6. Garoby R. Low Level RF Building Blocks. CERN Acceler-ator School 1991. CERN, Geneva, Switzerland. 428-4577. Ray Andraka. Andraka Consulting Group, Inc. 16 Arcadia Drive North Kingstown

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ZHAO Yu-Bin, YIN Cheng-Ke, ZHANG Tong-Xuan, FU Ze-Chuan, ZHAO Zhen-Tang, DAI Zhi-Min, LIU Jian-Fei and WANG Fang. Digital prototype of LLRF system for SSRF[J]. Chinese Physics C, 2008, 32(9): 758-760. doi: 10.1088/1674-1137/32/9/015

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Received: 2007-11-09
Revised: 2007-12-19

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通讯作者: 陈斌, bchen63@163.com

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沈阳化工大学材料科学与工程学院沈阳 110142

Digital prototype of LLRF system for SSRF

Corresponding author: ZHAO Yu-Bin,

Received Date: 2007-11-09

Accepted Date: 2007-12-19

Available Online: 2008-09-05

Abstract:

This paper describes a field programming gate array (FPGA) based low level radio frequency (LLRF) prototype for the SSRF storage ring RF system. This prototype includes the local oscillator (LO), analog front end, digital front end, RF out, clock distributing, digital signal processing and communication functions. All feedback algorithms are performed in FPGA. The long term of the test prototype with high power shows that the variations of the RF amplitude and the phase in the accelerating cavity are less than 1% and 1° respectively, and the variation of the cavity resonance frequency is controlled within ±10 Hz.

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Digital prototype of LLRF system for SSRF

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通讯作者: 陈斌, bchen63@163.com

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